2. Field of the Invention
This invention relates to the manufacture of integrated circuits and more particularly to the manufacture of microcontrollers.
3. Description of the Relevant Art
A microcontroller is an integrated circuit which incorporates a microprocessor core along with one or more support circuits on the same monolithic semiconductor substrate (i.e., chip). A typical computer system includes a microprocessor secured within its own semiconductor device package and connected to several separately-packaged support circuits. The support circuits perform support functions such as communication functions and memory interface functions. Computer systems which employ microcontrollers may thus be formed using fewer semiconductor devices. Advantages of such systems include lower fabrication costs and higher reliabilities. Microcontrollers find applications in industrial and commercial products including control systems, computer terminals, hand-held communications devices (e.g., cellular telephones), photocopier machines, facsimile machines, and hard disk drives.
A microcontroller is typically coupled to one or more external memory devices which store software programs consisting of instructions and data. During operation, the microcontroller fetches the instructions and data from the external memory devices and operates upon the data during instruction execution. The microprocessor core of the microcontroller typically includes an execution unit coupled to a bus interface unit (BIU). The BIU generates multiple address and control signals used to fetch the instructions and data from the external memory devices, and the execution unit executes those instructions. Each unique combination of the address signals generated by the BIU allows access to a different memory location within the external memory devices. For example, if the BIU generates n address signals, the microcontroller may access 2.sup.n unique memory locations.
Due to the widespread acceptance of the x86 microprocessor architecture, many microcontrollers include execution units which execute x86 instructions. While newer microcontrollers incorporate an increased number of support circuits, their execution units remain virtually unchanged in order to maintain backwards compatibility with the vast amount of existing software developed for previous microcontroller products.
There are two basic types of software programs: operating system programs and application programs. An operating system is a collection of software programs which provide file management, input/output control, and a controlled environment for executions of applications programs. MS-DOS.RTM. and Windows NT.TM. (Microsoft Corp.) are common operating systems. An application program is a computer program which performs a specific function, and is typically designed to operate within the controlled environment created by an operating system.
Early x86 microprocessors generate 20 address signals A0-A19. The simultaneous values of the address signals A0-A19 define an address, where A0 is the least significant bit of the binary value of the address and A19 is the most significant bit of the binary value of the address. The 20-bit addresses are generated from a 16-bit "segment" portion and a 16-bit "offset" portion. The segment portion is first shifted four bit positions to the left, then the offset portion is added to the shifted segment portion to form the 20-bit address. With 20 address lines, early x86 microprocessors could generate 2.sup.20 (i.e., 1,048,576) unique combinations of address signals and access 2.sup.20 unique memory locations (i.e., 1,048,576 8-bit bytes of memory, or 1 Mbyte of memory). Newer x86 microprocessors still retain this address generation capability in order to maintain software compatibility. The segment portion is stored in one of several dedicated segment registers which software instructions may read and write. The offset portion is typically generated by the execution unit during instruction execution. Microcontrollers based upon the x86 architecture employ this shift-and-add technique to generate 20-bit addresses. The BIU of such microcontrollers typically has special hardware to perform the shift-and-add address generation operation.
The memory address space of a microcontroller generating n address signals extends over 2.sup.n consecutive memory locations from memory location 0 to memory location 2.sup.n -1. For example, the memory address space of a microcontroller having 20 address lines extends from memory location 0 (00000h) to 2.sup.20 -1 (i.e., 1,048,575 or FFFFFh). The x86 architecture places certain restrictions upon the contents of memory locations within the memory address space. The x86 architecture reserves portions of the memory address space having the highest and lowest address values for operating system software. A first portion of the memory address having the highest address values (i.e., the uppermost portion of the memory address space) is reserved for software instructions executed following assertion of a RESET signal, system configuration data, and interrupt service routines executed following the reception of interrupt signals. A second portion the memory address space having the lowest address values (i.e., the lowermost portion of the memory address space) is also reserved for operating system software. The first 1,024 bytes of the memory address space (i.e., memory locations 0 through 1,023 or 003FFh) are reserved for an interrupt vector table including 256 4-byte addresses of the entry points of the interrupt service routines corresponding to received interrupt numbers.
Due to the requirement to reserve the uppermost and lowermost portions of the memory address space, microcontrollers employing the x86 architecture typically include a chip select unit (CSU) which generates separate chip select signals for the uppermost and lowermost portions of the memory address space. The CSU typically also generates one or more chip select signals for a middle portion of the memory address space existing between the uppermost and lowermost portions. Only one chip select signal is asserted at any given time, and only memory devices receiving an asserted chip select signal are enabled for the memory access operation in progress. A first non-volatile memory device (e.g., a ROM or a Flash device) typically contains the portion of the operating system software residing in the uppermost portion of the memory address space and receives the corresponding chip select signal. A second volatile memory device (e.g., a RAM device) typically contains the portion of the operating system software allocated to the lowermost portion of the memory address space and receives the corresponding chip select signal. Additional memory devices may contain application programs, and each additional memory device receives a chip select signal designated for the remaining middle portion of the memory address space.
For example, an x86-based microcontroller may be coupled to three different memory devices: a first 256K.times.8 Flash memory device, a second 256K.times.8 static random access memory (SRAM) device, and a third 512K.times.8 SRAM memory device. The first memory device has 18 address signal terminals MA0-MA17 and contains the portion of the operating system software residing in the uppermost portion of the memory address space. Terminals MA0-MA17 of the first memory device are connected to address signal terminals A0-A17 of the microcontroller, and the first memory device is enabled by a programmed upper chip select signal (UCS#). Chip select signal UCS# is an active low signal as denoted by the `#` symbol following the signal name `UCS`. Active low signals are asserted when driven to a low logic level and deasserted when driven to a logic high level. The second memory device also has 18 address signal terminals MA0-MA17, and contains the portion of the operating system software residing in the lowermost portion of the memory address space. Terminals MA0-MA17 of the second memory device are also connected to address signal terminals A0-A17 of the microcontroller, and the second memory device is enabled by a programmed lower chip select signal (LCS#). The third memory device has 19 address terminals MA0-MA18 and is allocated for applications programs. Terminals MA0-MA18 of the third memory device are connected to address signal terminals A0-A18 of the microcontroller, and the third memory device is enabled by a programmed middle chip select signal (MCS#). The CSU asserts signal UCS# when address values 786,432 (C0000h) through 1,048,575 (FFFFFh) are driven upon the address signal terminals, asserts signal LCS# when address values 0 (00000h) through 262,143 (3FFFFh) are driven upon the address signal terminals, and asserts signal MCS# when address values262,144 (40000h) through 786,431 (BFFFFh) are driven upon the address signal terminals.
Application programs tend to grow larger with time as new functions are added. In addition, each hardware support function incorporated within a microcontroller typically requires additional instructions for configuration and operation. At the same time, software compatibility requires that the number of address lines and the method of address signal generation remain the same. As a result, increasing the amount of memory accessible by a microcontroller is a problem often requiring unique solutions.
One common solution has been to replace a "smaller" memory device with a "larger" memory devices having a greater number of memory locations and requiring additional address signals. The microcontroller coupled to the larger memory devices generates additional control signals which function as the additional address signals. Special software is used to generate the additional control signals. The additional control signals typically form the most significant address signals, dividing the larger memory device into multiple sections or "banks" of memory. All of the memory banks created in this fashion have the same number of memory locations (i.e., are the same size). The additional control signals select between the available memory banks, determining which of the memory banks is active.
For example, the third memory device in the above example may be replaced by a 1024K.times.8 memory device having 20 address signal terminals MA0-MA19. If terminals MA0-MA19 of the third memory device were connected to respective address signal terminals A0-A19 of the microcontroller, the portions of the third memory device which overlap the uppermost and lowermost portions of the memory address space (i.e., half the memory locations within the third memory device) would not be accessible as the MCS# signal would not be asserted during memory accesses involving these portions. However, by connecting terminals MA0-MA18 of the third memory device to respective address signal terminals A0-A18 of the microcontroller and connecting an additional control signal generated by the microcontroller to terminal MA19, the microcontroller may access all of the memory locations within the third memory device. This configuration creates two separate memory banks within the third memory device, each memory bank containing 512K memory locations. Special software executed by the microcontroller is used to generate the additional control signal, thereby selecting between the two memory banks.
The requirement of the x86 architecture to reserve portions of the memory address space creates problems when adding memory devices with capacities which exceed the available chip select ranges and contain memory locations with addresses within (i.e., mapped to) reserved portions of the memory address space. In this case, any of the memory banks mapped to a reserved portion of the memory address space may be active when the RESET signal is asserted or when an interrupt occurs. The most straightforward solution to this problem is also the least desirable: duplicate the applicable operating system software in each memory bank. The RESET signal assertion problem may be overcome by ensuring the additional control signals are driven to a logic high level (i.e., a logic 1) when the RESET signal is asserted. However, each memory bank mapped to the lowermost portion of the memory address space must contain a copy of the 1,024-byte interrupt vector table, and each memory bank mapped to the uppermost portion of the memory address space must include interrupt service routines which are either complete or include enough instructions to switch to a "common" memory bank containing the interrupt service routines.
For example, assume an x86-based microcontroller is coupled to two different memory devices: a first 256K.times.8 Flash memory device and a second 1,024.times.8 SRAM memory device. The first memory device has 18 address terminals MA0-MA17 and contains the portion of the operating system software residing in the uppermost portion of the memory address space. Terminals MA0-MA17 of the first memory device are connected to respective address signal terminals A0-A17 of the microcontroller, and the first memory device is enabled by a programmed upper chip select signal (UCS#). The second memory device has 20 address terminals MA0-MA19, and contains the portion of the operating system software residing in the lowermost portion of the memory address space. The remainder of the second memory device is available for application programs.
In order for the microcontroller to access to all of the memory locations within the second memory device, terminals MA0-MA18 of the second memory device are connected to respective address signal terminals A0-A18 of the microcontroller, the microcontroller generates an additional control signal connected to terminal MA19, and the second memory device is enabled by a programmed lower chip select signal (LCS#). The CSU asserts signal UCS# when address values 786,432 (C0000h) through 1,048,575 (FFFFFh) are driven upon the address signal terminals, and asserts signal LCS# when address values 0 (00000h) through 524,287 (7FFFFh) are driven upon the address signal terminals. The second memory device contains two memory banks each containing 512K memory locations mapped between address values 0 (00000h) and 524,287 (7FFFFh). Special software executed by the microcontroller generates the additional control signal, thereby selecting between the two memory banks. However, as a result of the requirement of the x86 architecture to reserve portions of the memory address space, both memory banks must contain a copy of the 1,024-byte interrupt vector table in memory locations corresponding to address values 0 (00000h) through 1,023 (003FFh).
Dynamic random access memory (DRAM) devices, offering comparatively large numbers of memory locations in small packages at low costs, are commonly used in computer systems. DRAM devices employ address signal multiplexing in order to reduce the number of required address pins. While non-DRAM (e.g., SRAM devices and Flash memory devices) typically have log.sub.2 (n) address signal terminals (i.e., pins), where n is the number of memory locations within the device, DRAM devices have a much smaller number of address pins. Addresses of memory locations within DRAM devices are typically divided into two portions of nearly equal length. A first portion of the address is made up of the most significant bits of the address and is called the row address. The remaining portion is called the column address. During a memory access operation involving a DRAM device, the row address is first conveyed to the address pins, and a row address strobe (RAS#) signal is asserted to store the row address within the DRAM device. The column address is then conveyed to the address pins, and a column address strobe (CAS#) signal is asserted to store the column address within the DRAM device. If the memory access operation is a read operation, the contents of the accessed memory location are driven upon one or more data pins of the DRAM device. If the memory access operation is a write operation, logic values present upon the data pins are stored within the accessed memory location. Computer systems employing DRAM devices typically include a memory controller which generates the multiplexed address signals and the control signals required by the DRAM devices.
It would be beneficial to have a microcontroller which includes additional hardware to generate address signals which provide for memory banking. When access to operating system software is desired, the address signals select a single memory bank containing the operating system software. Such a microcontroller would eliminate the need to duplicate operating system software in each memory bank mapped to a reserved portion of the memory address space, allowing efficient utilization of larger memory devices. Furthermore, it would be beneficial for the additional hardware to produce the address signals in a multiplexed fashion along with the control signals required by DRAM devices such that both non-DRAM devices (e.g., SRAM devices or Flash memory devices) and DRAM devices may be coupled to the microcontroller. It would also be beneficial for the microcontroller to achieve the above while maintaining software compatibility with previous microcontroller products.